Texas Instruments 74HC73 Dual JK Flip-Flop IC, Negative-Edge Triggered, 14-Pin
Texas Instruments 74HC73 dual negative-edge triggered JK flip-flop IC with asynchronous reset, 14-pin DIP package and complementary outputs.
Texas Instruments 74HC73 Dual JK Flip-Flop IC is a dual negative-edge triggered JK flip-flop built on high-speed CMOS logic, with a 14-pin DIP package for digital designs.
The 74HC73 provides individual J and K data inputs, clock inputs, and complementary Q and Q outputs for each device. State changes occur on the negative-going (falling) edge of the clock pulse. An asynchronous reset is achieved through a low-level input, allowing the outputs to be cleared independently of the clock signal.
Key Features
- Hysteresis on the clock inputs improves performance in noisy environments and allows increased input rise and fall times.
- Asynchronous reset clears the flip-flop outputs regardless of the clock state.
- Capable of driving up to 10 LSTTL loads, simplifying interfacing with other logic families.
- Buffered inputs and balanced propagation delay and transition times for reliable signal integrity.
- Substantial reduction in power consumption compared with equivalent LSTTL integrated circuits.
Compatibility and Package
The HCT logic family variant provides full functional and pin compatibility with standard LS TTL logic, facilitating upgrades in existing systems. The device is functionally identical to the HC/HCT107 but differs in terminal assignments.
The device is supplied in a standard 14-pin DIP (Dual In-line Package) format. Its design includes protection against high-current conditions, with ratings specified for DC input/output diode current and DC drain current.
Specify the Texas Instruments 74HC73 when a dual negative-edge triggered JK flip-flop with asynchronous reset, complementary outputs, and HCT compatibility with standard LS TTL logic is required.
- Modern digital designs
- Upgrading existing systems with LS TTL logic
- Interfacing with other logic families
- Logic Family: HC/HCT CMOS
- Trigger: Negative-edge triggered
- Reset: Asynchronous, active low
- Outputs: Complementary Q and Q
- Output Drive: Up to 10 LSTTL loads
- Special Feature: Hysteresis on clock inputs
- Special Feature: Buffered inputs
- Compatibility: Functionally identical to HC/HCT107 with different terminal assignments
- Compatibility: Pin compatible with standard LS TTL logic (HCT variant)
- Package: 14-pin DIP (Dual In-line Package)
- Width: 3.3
- Depth: 1.5
- Height: 4.3
- Weight: 1.667 g
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