NXP PCA9517ADP Level Translating I2C Bus Repeater TSSOP-8

The NXP PCA9517ADP Level Translating I2C Bus Repeater offers two-channel bidirectional buffering, with up to 400 pF on each side of the device, for mixed-voltage I2C-bus and SMBus systems.

Overview

The NXP PCA9517ADP is a CMOS integrated circuit designed for level translation between low-voltage (down to 0.9 V) and higher-voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications. It retains all standard I2C operating modes while extending the bus through bidirectional buffering of the SDA and SCL lines, enabling robust communication across two bus segments.

The device isolates two halves of a bus for both voltage level and capacitive load, offering design flexibility. The SDA and SCL pins are overvoltage tolerant and remain high-impedance when the device is unpowered. The port A drivers, which interface with the adjustable lower-voltage bus, deliver more current and eliminate static offset voltage. A low signal on the higher-voltage port B is translated into a near 0 V low on port A, suiting the smaller voltage swings of lower-voltage logic.

Key Features

• Bidirectional buffering: two-channel buffer isolates capacitance, permitting 400 pF on either side of the device.
• Compatibility: fully compatible with I2C-bus and SMBus standards.
• Control: active-high repeater enable input for easy master control.
• Interface: open-drain input/outputs.
• Reliable operation: designed for lock-up free operation, supporting arbitration and clock stretching across the repeater.
• Device support: accommodates Standard-mode and Fast-mode I2C-bus devices and supports systems with multiple masters.
• Robust pins: I2C-bus and enable pins are 5 V tolerant, and I2C-bus pins are high-impedance when powered off.
• Latch-up testing: performed to JEDEC Standard JESD78, exceeding 100 mA.

Specifications

• Package: TSSOP-8
• Width: 3.3
• Depth: 1.5
• Height: 4.3
• Weight: 0.091 g

This integrated circuit suits designers bridging mixed-voltage I2C-bus systems.