NXP CMOS Decoder/Demultiplexer SOIC16

This high-speed Si-gate CMOS device functions as a decoder and demultiplexer, offering pin compatibility with low power Schottky TTL (LSTTL). The decoder accepts three binary weighted address inputs (A0, A1 and A3) and, when enabled, provides eight mutually exclusive active LOW outputs (Y0 to Y7).

This integrated circuit features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output remains HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows for easy parallel expansion to a 1-of-32 (5 lines to 32 lines) decoder using just four of these ICs and one inverter.

The device can also serve as an eight-output demultiplexer by utilising one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Any unused enable inputs should be permanently tied to their appropriate active HIGH or LOW state.

Featuring demultiplexing capability and multiple input enables, this component complies with JEDEC standard no. 7A and is ideal for memory chip select decoding. It also offers robust ESD protection, with Human Body Model (HBM) exceeding 2000V and Machine Model (MM) exceeding 200V.

Key Features

• High-speed Si-gate CMOS logic
• 8 active LOW mutually exclusive outputs
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Complies with JEDEC standard no. 7A
• HBM ESD protection exceeds 2000V
• MM ESD protection exceeds 200V

With an operating temperature range of -40°C to 125°C and a supply voltage between 2V and 6V, this logic IC is highly versatile. The product dimensions are 43 mm in height, 33 mm in width, and 15 mm in depth, with a lightweight design of just 0.6 grams.